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DS3832C-311
3.3V, 32Mb Advanced NV SRAM with Clock
www.maxim-ic.com
FEATURES
3.0V to 3.6V operation Surface-mount nonvolatile (NV) RAM ball-grid array (BGA) module construction 1024k x 32 NV SRAM memory space and separate 64 x 8 real-time clock (RTC) memory space RTC maintains hundredths of seconds, seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100 Removable backup power source provides more than eight years of timekeeping and data retention Read and write access times as fast as 100ns for NV SRAM memory and 200ns for RTC Automatic data protection during power loss Unlimited write-cycle endurance Low-power CMOS operation Battery monitor checks remaining capacity daily Industrial temperature range of -40C to +85C
PACKAGE OUTLINE

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DESCRIPTION
The DS3832C-311 is a 1,048,576 x 32 advanced NV SRAM module with a 168-bump BGA pinout. The highly integrated DS3832C-311 contains a 64-byte RTC, four 8Mb SRAMs, and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the DS3832C311 makes use of an attached DS3802 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS3832C-311 has dedicated circuitry for monitoring the status of VCC and the status of an attached DS3802 battery cap.
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081602
DS3832C-311
PIN ASSIGNMENT (With Overlaid Package Outline) Figure 1
Because the DS3832C-311 has a total of 168 balls and only 76 active signals, balls are wired together into numbered groups, thus providing redundant connections for every signal.
CEC OE WEC WE1 CE1 OEC CE3 A10 A11 A8 A9 A0 WE3 A1 A2 A3 A4 VCC 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 CEO 78 VCC BW 80 79
VBAT
GND
A15 A17 A13 A18 WE0 A16 A14 A12 A7 A6 A5 DQ7 DQ6 DQ5 RSV2 A19 DQ4 DQ0 DQ1 DQ2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
DS3832C-311
RECEPTACLES FOR DS3801 RECEPTACLES FOR DS3802 BATTERY CAP PINS BATTERY CAP PINS 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
CE2 DQ31 DQ30 DQ29 WE2 DQ28 DQ27 DQ24 DQ25 DQ26 DQ16 DQ17 DQ18 DQ23 RSV1 DQ22 DQ21 DQ20 DQ19
GND GND DQ3 DQC3 DQC4 DQC5 NC DQC6 DQC7 DQC0 DQC1 DQC2 DQ10 DQ9 DQ8 DQ15 INT DQ14 DQ13 DQ12 DQ11 GND
VBAT
PIN DESCRIPTION
A19 to A0 - Address Inputs DQ31 to DQ0 - NV SRAM Data In/Data Out DQC7 to DQC0 - Clock Data In/Data Out CE3 to CE0 - NV SRAM Chip-Enable Inputs CEC - Clock Chip-Enable Input WE3 to WE0 - NV SRAM Write-Enable Inputs WEC - Clock Write-Enable Input OE - NV SRAM Output-Enable Input - Clock Output-Enable Input - Battery Warning Output - Interrupt Output VCC - Power (3.3V) GND - Ground RSV1 - No Connect VBAT - DS3802 Battery Cap Connection
OEC BW INT
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DS3832C-311
BLOCK DIAGRAM Figure 2
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DS3832C-311
NV SRAM READ MODE
The DS3832C-311 executes an NV SRAM read cycle whenever WE0 to WE3 (write enables) are inactive (high), any or all of CE0 to CE3 (chip enables) are active (low) and OE (output enable) is active (low). The unique address specified by the 20 address inputs (A0 to A19) defines which of the 1,048,576 words of data is accessed. The four chip-enable signals ( CE0 to CE3 ) determine which bytes in the addressed word are output on data lines DQ31 to DQ0. Valid data will be output within tACC (NV SRAM access time) after the last address input signal is stable, providing that CE and OE (output enable) access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than tACC.
NV SRAM WRITE MODE
The DS3832C-311 executes an NV SRAM write cycle whenever any or all of the WE signals ( WE0 to WE3 ) are active (low) and any of the corresponding CE \ signals ( CE0 to CE3 ) are active (low) after all address inputs are stable. The later occurring falling edge of CE or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE0 to WE3 must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if output drivers are enabled ( CE and OE active) then WE disables the outputs in tODW from its falling edge.
CLOCK READ MODE
The DS3832C-311 executes a clock read cycle whenever WEC (clock write enable) is inactive (high), CEC (clock chip enable) is active (low), and OEC (output enable) is active (low). The unique clock address specified by address inputs A0 to A5 defines which of the 64 bytes of data is accessed. Valid data is output within tACC (clock access time) after the last address input signal is stable, providing that CEC and OEC (output enable) access times are also satisfied. If CEC and OEC access times are not satisfied, then data access must be measured from the later occurring signal ( CEC or OEC ) and the limiting parameter is either tCO for CEC or tOE for OEC rather than tACC. Only addresses 0 to 3Fh are implemented in the clock address space. Accesses to clock addresses higher than 3Fh are undefined.
CLOCK WRITE MODE
The DS3832C-311 executes a clock write cycle whenever WEC is active (low) and CEC is active (low) after all address inputs are stable. The later occurring falling edge of CEC or WEC determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CEC or WEC . All address inputs must be kept valid throughout the write cycle. WEC must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OEC control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if output drivers are enabled ( CEC and OEC active) then WEC disables the outputs in tODW from its falling edge.
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DS3832C-311
DATA RETENTION MODE
The DS3832C-311 provides full functional capability for VCC greater than 3.0V and write protects by 2.8V. Data is maintained in the absence of VCC without any additional support circuitry. The DS3832C311 constantly monitors VCC. Should the supply voltage decay to VTP, the device automatically write protects itself, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 2.8V, a power-switching circuit electrically connects an attached DS3802 battery cap to the SRAM to retain data. During power-up, when VCC rises above approximately 2.8V, the powerswitching circuit connects external VCC to the SRAM and disconnects the DS3802 normal RAM operation can resume after VCC reaches the minimum power-supply voltage.
BATTERY MONITORING
The DS3832C-311 automatically monitors the battery in an attached DS3802 battery cap on a 24-hour time interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1MW test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the battery cap or DS3802 is replaced. The battery is still retested after each VCC power-up even if BW is active. If the battery voltage is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing resumes. BW has an open-drain output driver.
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DS3832C-311
CLOCK REGISTERS Figure 3
ADDRESS 0 1 2 3 4 CLOCK, CALENDAR, TIME-OF-DAY ALARM REGISTERS 0 0 M 0 BIT 7 0.1 SECONDS 10 SECONDS 10 MINUTES 10 MIN ALARM 12/24 10 A/P 10 HR 10 HR 0 0 0 0 0.01 SECONDS SECONDS MINUTES MIN ALARM HOURS BIT 0 RANGE 00 to 99 00 to 59 00 to 59 00 to 59 01 to 12 + A/P or 00 to 23 01 to 12 + A/P or 00 to 23 01 to 07 01 to 07 01 to 31 01 to 12 00 to 99 TDF
5
M
12/24
10 A/P
HR ALARM
6 7 8 9 A COMMAND REGISTER B
0 M INP EOSC
0 0 0 ESQW
0 0 10 DATE 0
DAYS DAY ALARM DATE MONTHS YEARS
10 MO
10 YEARS TE IPS W HI/LO PU/LVL WAM
TDM
WAF
WATCHDOG ALARM REGISTERS
C D E 3F
0.1 SECONDS 10 SECONDS
0.01 SECONDS SECONDS
00 to 99 00 to 99
USER REGISTERS
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DS3832C-311
TIME-OF-DAY ALARM MASK BITS (Figure 4)
MINUTES REGISTER HOURS DAYS ALARM
1 0 0 0
1 1 0 0
1 1 1 0
ALARM ONCE PER MINUTE ALARM WHEN MINUTES MATCH ALARM WHEN MINUTES AND HOURS MATCH ALARM WHEN MINUTES, HOURS, AND DAYS MATCH
NOTE:
Any other bit combinations produce illogical operation.
CLOCK REGISTERS
The DS3832C-311 clock has 14 8-bit internal registers that contain all timekeeping, alarm, watchdog, and control information. The clock, calendar, alarm, and watchdog registers are memory locations that contain both external (user-accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by simultaneous transfer from the incremented internal copies. The command register bits are affected by both internal and external functions. In addition to the 14 registers, the clock also contains 50 bytes of user RAM. Clock registers 0, 1, 2, 4, 6, 8, 9, and A (hex) contain day, date, and time information stored in binary-code decimal (BCD) format. Registers 3, 5, and 7 contain time-of-day alarm information also stored in BCD format. Register B is the command register containing eight 1-bit binary fields. Registers C and D contain watchdog alarm information stored in BCD format. Addresses E through 3F are general-purpose user RAM.
DAY, DATE AND TIME REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9, and A (hex) contain day, date, and time information in BCD format. Eleven bits within these eight registers are not used and will always read zero regardless of how they are written. Bits 6 and 7 in the month register (register 9) are binary control bits. When set to logic 0, EOSC (register 9, bit 7) enables the clock oscillator. This bit is normally turned on by the user during device initialization. The oscillator can be turned on and off as needed by enabling or disabling this bit. Register 8 bit 7, INP, controls the logic state of the INTP output pin of the clock device. Because this logic feature is not supported in the DS3832C-311, INP should be set to a logic zero. Register 9 bit 6, ESQW , enables and disables the output of a 1024Hz square wave. Because this feature is not supported in the DS3832C-311, ESQW should be set to logic one. Bit 6 of the hour register (register 4) is defined as the 12- or 24-hour select bit. When set to logic one, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the upper-order 10-hour bit (set for hours 20 to 23). The external day, date, and time registers are updated from their internal counterparts every 0.01 seconds except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running ( EOSC high). Setting TE low freezes the external day, date, and time registers at their present values allowing all the registers to be read or written without any of them being updated from the internal registers. After the
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DS3832C-311
registers have been read or written, setting TE high re-enables external register updates. While TE is set low and the external registers are frozen, the internal registers continue to be incremented.
TIME-OF-DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the time-of-day alarm registers. Bits 3, 4, 5, and 6 of register 7 always read zero regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (see Figure 4). When all of the mask bits are logic 0, a time-of-day alarm only occurs when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. An alarm is generated every day when bit 7 of register 7 is set to logic 1. Similarly, an alarm is generated every hour when registers 7 and 5 both have bit 7 set to logic 1. When registers 7, 5, and 3 all have bit 7 set to logic 1, an alarm occurs every minute at the point where register 1 (seconds) rolls over from 59 to 00. Whenever an alarm occurs, the time-of-day alarm flag TDF (register B, bit 0) and the internal time-of-day interrupt signal goes to the active state. If the interruptswitch bit IPSW (register B, bit 6) is set to a logic 0 and the time-of-day alarm mask bit TDM (register B, bit 3) is logic 0, the interrupt-output pin INT also activates. Time-of-day alarm registers are written and read in the same format as the day, date, and time registers. The time-of-day alarm flag, time-of-day interrupt, and INT output are always cleared when the time-ofday alarm registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the timeout period for the watchdog alarm. The two registers contain a count from 0.01 to 99.99 seconds in BCD format. The two watchdog alarm registers can be written or read in any order. After a new value is entered or either of the watchdog alarm registers is read, an internal watchdog timer starts counting down from the entered watchdog alarm register value toward zero. When zero is reached, the watchdog alarm flag (register B, bit 1) and the internal watchdog interrupt signal go to the active state. If the interrupt switch bit IPSW (register B bit 6) is set to logic 1 and the watchdog alarm mask bit WAM (register B, bit 3) is logic 0, the interrupt output INT also activates. The watchdog timer countdown is interrupted and the timer is re-initialized to the value in the watchdog alarm registers every time either watchdog alarm register is accessed. Controlled, periodic accesses to the watchdog alarm registers can prevent the activation of the watchdog alarm flag, the internal watchdog interrupt signal and the INT output. The watchdog alarm registers always read the value entered. The actual watchdog timer is internal and is not accessible. Writing 00h to registers C and D disables the watchdog alarm feature.
COMMAND REGISTER
Register B, the command register, contains control bits and flag bits. The operation of each bit is described below. TE--Transfer Enable (Bit 7). When set to logic 0, this bit disables the transfer of data between internal and external clock registers. The contents of the external registers are frozen and reads and writes of day, date, and time information are not affected by updates. This bit must be set to logic 1 to enable updates. IPSW--Interrupt Switch (Bit 6). This bit should be initialized to logic 1 to connect the internal watchdog interrupt signal to the INT output pin. Setting this bit to logic 0 connects the internal time-ofday interrupt signal to the INT output pin.
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DS3832C-311
HI/LO-- INT Sink or Source Current (Bit 5). When this bit is set to logic 1 and VCC is applied, the INT output pin will source current when activated (see IOH spec). When this bit is set to logic 0, INT sinks current (see IOL spec). PU/LVL-- INT Pulse or Level (Bit 4). When this bit is set to logic 0, INT is in the level mode, going to the logic level defined by the HI/LO bit and staying there until the interrupt is cleared. When this bit is set to logic 1, INT is in pulse mode, sourcing or sinking current as defined by the HI/LO bit for a minimum of 3ms and then releasing. WAM--Watchdog Alarm Mask (Bit 3). When this bit is set to logic 0, the internal watchdog interrupt signal is enabled. If IPSW is also set to logic 1, any watchdog alarm activates the INT output. When this bit is set to logic 1, watchdog alarms have no effect on the internal watchdog interrupt signal or on the INT pin. TDM--Time-of-Day Alarm Mask (Bit 2). When this bit is set to logic 0, the internal time-of-day interrupt signal is enabled. If IPSW is set to logic 0, any time-of-day alarm activates the INT output. When this bit is set to logic 1, time-of-day alarms have no effect on the internal time-of-day interrupt signal or on the INT pin. WAF--Watchdog Alarm Flag (Bit 1). This bit is set to logic 1 when a watchdog alarm occurs (regardless of the state of the watchdog alarm mask bit WAM). WAF is read-only. This bit is reset when either of the watchdog alarm registers is accessed. When the PU/LVL bit is in the pulse mode, this flag is only set to logic 1 for the 3ms duration of the INT output pulse. TDF--Time-of-Day Alarm Flag (Bit 0). This bit is set to logic 1 when a time-of-day alarm occurs (regardless of the state of the time-of-day alarm mask bit TDM). TDF is read-only. The time the alarm occurred can be determined by reading the time-of-day alarm registers. This bit is reset to logic 0 when any of the time-of-day alarm registers is accessed. When the PU/LVL bit is in the pulse mode, this flag is only set to logic 1 for the 3ms duration of the INT output pulse.
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DS3832C-311
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3 to +4.6 V -40C to +85C -40C to +85C See IPC/JEDEC J-STD-020A Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Logic 1 Input Voltage Logic 0 Input Voltage SYMBOL VCC VIH VIL MIN 3.0 2.2 0 TYP 3.3 MAX 3.6 VCC 0.6
(TA = -40C to +85C)
UNITS V V V NOTES 1 1 1
DC ELECTRICAL CHARACTERISTICS (TA = -40C to +85C; VCC= 3.3V 0.3V)
PARAMETER Input Leakage Current I/O Leakage Current Output Current at 2.4V Output Current at 0.4V Standby Current (All CE = VIH) Standby Current (All CE = VCC - 0.3V) Operating Current (One CE = VIL) Operating Current (All CE = VIL) Write Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 ICCO2 VTP 2.8 2.9 MIN -5 -1 -1 2 TYP MAX 5 1 UNITS mA mA mA mA mA mA mA mA V 4 4 NOTES
5 2
7 5 50 200 3.0
CAPACITANCE
PARAMETER Input Capacitance: A19 to A0, OE Input Capacitance: CE3 - CE0 , WE3 - WE0 , CEC ,
WEC , OEC
(TA = +25C)
SYMBOL CIN CIN CI/O COUT MIN TYP 25 5 5 5 MAX 50 10 10 10 UNITS pF pF pF pF NOTES
I/O Capacitance: DQ31-DQ0, DQC7-DQC0 Output Capacitance: BW ,
INT
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DS3832C-311
AC ELECTRICAL CHARACTERISTICS (TA = -40C to +85C; VCC= 3.3V 0.3V)
PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High-Z from Deselection Output Hold from Address Change Write Cycle Time CE Pulse Width Write Pulse Width Address Setup Time Write Recovery Time Output High-Z from
WE
SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tCW tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
NV SRAM MIN MAX 100 100 50 100 5 35 5 100 100 75 0 5 20 35 5 40 0 20
CLOCK MIN MAX 200 200 70 200 5 50 5 200 200 150 0 15 20 50 5 100 0 20
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES
6 6
12 13 6 6 5 12 13
Output Active from
WE
Data Setup Time Data Hold Time
TIMING DIAGRAM: READ CYCLE
tRC
ADDRESS tACC CEX tCO tOD OEX tCOE DOUT tOE tCOE tOD OUTPUT DATA VALID tOH
See Note 2.
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DS3832C-311
TIMING DIAGRAM: WRITE CYCLE 1 (WE)
tWC ADDRESS tAW CEX tCW tWR1 WEX tWP
tODW DOUT tDS DIN
tOEW
tDH1
INPUT DATA STABLE
See Notes 3, 5, 7, 8, 9, and 12.
TIMING DIAGRAM: WRITE CYCLE 2 (CE)
tWC
ADDRESS
tAW CEX
tCW
tWR2
WEX
tWP
tCOE DOUT
tODW
tDS DIN
tDH2
INPUT DATA STABLE
See Notes 3, 5, 7, 8, 9, and 13.
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DS3832C-311
POWER-DOWN/POWER-UP CONDITION
VCC VTP 2.7V tF tPD CEX, WEX
SLEWS WITH VCC
tR tPU tREC
BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY
tDR
SLEWS WITH VCC
tBPU
BW\
See Note 11.
TIMING DIAGRAM: BATTERY WARNING DETECTION
VCC tBPU VBAT 2.6V tBTC tBTPW
BATTERY TEST ACTIVE
tBW BW
See Note 14.
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DS3832C-311
POWER-DOWN/POWER-UP TIMING
PARAMETER SYMBOL tPD VCC Fail Detect to CE and WE\ Inactive VCC Slew from VTP to 0V tF VCC Slew from 0V to VTP tR tPU VCC Valid to CE and WE Inactive VCC Valid to End of tREC Write Protection VCC Valid to BW Valid tBPU INT Pulse Width tIPW (PU/LVL Bit High) MIN TYP MAX 0
(TA = -40C to +85C)
UNITS ms ms ms ms ms s ms 14 15 NOTES 11
300 300 2 125 1 3
BATTERY WARNING TIMING
PARAMETER Battery Test Cycle Battery Test Pulse Width Battery Test to BW Active SYMBOL tBTC tBTPW tBW MIN
(TA = -40C to +85C; VCC = 3.3V 0.3V)
TYP 24 MAX 1 1 UNITS hr s s NOTES
(TA = +25C)
PARAMETER Expected Data Retention Time SYMBOL tDR MIN 8 TYP MAX UNITS years NOTES 10
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when this device is in battery backup mode.
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DS3832C-311
NOTES:
All voltages referenced to ground. WE is high throughout read cycle. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. All outputs open-circuited. tDS is measured from the earlier of CE or WE going high. These parameters are sampled with a 5pF load and are not 100% tested. If the CE low transition occurs simultaneously with, or later than, the WE low transition, the output buffers remain in a high-impedance state during this period. 8) If the CE high transition occurs prior to, or simultaneously with, the WE high transition, the output buffers remain in a high-impedance state during this period. 9) If WE is low or the WE low transition occurs prior to, or simultaneously with, the CE low transition, the output buffers remain in a high-impedance state during this period. 10) Expected data retention time can be extended indefinitely if the DS3802 battery cap is periodically replaced. 11) In a power-down condition, the voltage on any pin may not exceed the voltage on VCC. 12) tWR1, tDH1 are measured from WE going high. 13) tWR2, tDH2 are measured from CE going high. 14) BW is an open-drain output and cannot source current. An external pullup resistor should be connected to this pin for proper operation. This pin sinks 10mA. 15) INT activates within 100ns after the alarm condition arises. 1) 2) 3) 4) 5) 6) 7)
DC TEST CONDITIONS
Outputs Open All voltages are referenced to ground
AC TEST CONDITIONS
Output load: 100pF + 1 TTL gate Input pulse levels: 0V to 2.7V Timing measurement reference levels Input: 1.5V Output: 1.5V Input pulse rise and fall times: 5ns
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DS3832C-311
DS3832C-311 PACKAGE DIMENSIONS
A B C D E F G H I J K DIM in mm in mm in mm in mm in mm in mm in mm in mm in mm in mm in mm MIN 1.720 43.69 1.720 43.69 0.108 2.74 1.497 38.02 0.047 1.19 0.108 2.74 0.047 1.19 0.305 7.74 0.125 3.10 0.025 0.64 MAX 1.730 43.94 1.730 43.94 0.118 3.00 1.503 38.18 0.053 1.35 0.118 3.00 0.053 1.35 0.320 8.13 0.135 3.43 .135 3.43 0.032 0.76
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DS3832C-311
DS3832C-311 PACKAGE DIMENSIONS (With Attached DS3802 Battery Cap)
DIM in mm B in mm C in mm D in mm A MIN MAX 1.830 45.046 1.830 45.046 0.435 10.708 0.0390 0.9600
A
B
C
D
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DS3832C-311
DS3832C-311 RECOMMENDED LAND PATTERN (With Overlaid Package Outline)
The DS3832C-311 ball grid array is a subset of the industry-standard 40mm BGA format, with all balls on a 50mil grid. Corner balls have been removed to provide space for the electrical and mechanical interface features that facilitate attachment of the DS3802 battery cap
V-BAT TEST PADS 0.027 DIA 2 PL
I/O PADS 0.27 DIA X 168 PL 0.113
0.150
80 79 78 7776 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60
0.050 TYP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
1.500
1.725 sq.
20 21 22 23 24 25 26 27 28 29 3031 32 33 34 35 36 3738 39 40
0.413
0.050 TYP
0.113
0.150
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